异步时序逻辑电路的分析与设计
摘 异步时序逻辑电路状态改变须考虑外部输入信号应存储器时钟端或控制端无信号作用这分析设计个难点针这难点进行详细讨论系统框图给出分析设计般步骤总结分析设计中般问题解决方法应注意问题举例验证方法正性通用性快速性关键词 异步时序逻辑电路 分析设计 系统框图 方法中图分类号TN79+1 文献标志码A 文章编号1006-8228201405-19-04Abstract One difficult point of analyzing and designing is that the external input signal the corresponding memory clock terminal and whether there are signal functions in control terminal has to be considered in changing the asynchronous logic circuit state. How solve this problem is discussed in detail. The general steps of analysis and design are given through system frame graphs. The solution of general problems in analysis and design and points that should be paid attention are summarized. The validity the versatility and speed of the method are verified by examples.Key words asynchronous sequential logic circuit analysis and design system chart method0 引言异步时序电路状态改变须考虑外部输入信号应存储器时钟端
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